zvec/python/tests
ihb2032 df447a54e2
Refactor CPU feature detection to use an explicit x86 whitelist (#258)
* fix(cpu_features): refactor architecture detection to explicit x86 whitelist

Currently, `cpu_features.cc` assumes any non-ARM architecture is x86/x64, which leads to a fatal missing `<cpuid.h>` error on architectures like RISC-V.
This commit refactors the preprocessor macros to explicitly whitelist x86 architectures (`__x86_64__`, `__i386__`, `_M_X64`, `_M_IX86`). All other architectures (RISC-V, ARM, etc.) will now safely fall back to the default zero-initialization, allowing cross-compilation to succeed.

Signed-off-by: ihb2032 <hebome@foxmail.com>

* ci: Add RISE RISC-V runner

Introduce the RISC-V CI runner provided by the RISE project.
This enables automated testing and building for the RISC-V architecture.

Signed-off-by: ihb2032 <hebome@foxmail.com>

* ci: use python 3.12 for RISC-V64

Signed-off-by: ihb2032 <hebome@foxmail.com>

* ci: add RISC-V numpy dependencies

Signed-off-by: ihb2032 <hebome@foxmail.com>

* ci: add RISC-V wheel cache

Signed-off-by: ihb2032 <hebome@foxmail.com>

* ci: use pre-built RISE numpy wheel to speed up riscv builds

Signed-off-by: ihb2032 <hebome@foxmail.com>

* ci: use pre-built RISE cmake wheel to speed up riscv builds

Signed-off-by: ihb2032 <hebome@foxmail.com>

* ci: split RISC-V build and test into separate jobs

Signed-off-by: ihb2032 <hebome@foxmail.com>

* ci: fix

Signed-off-by: ihb2032 <hebome@foxmail.com>

* ci: fix

Signed-off-by: ihb2032 <hebome@foxmail.com>

* Update hnsw_streamer_test.cc

* ci: add cache

Signed-off-by: ihb2032 <hebome@foxmail.com>

* Update hnsw_streamer_test.cc

* Update test_gil_release.py

* ci: schedule workflow to run overnight

---------

Signed-off-by: ihb2032 <hebome@foxmail.com>
Co-authored-by: ZeFeng Yin <yinzefeng.yzf@alibaba-inc.com>
2026-06-02 11:51:25 +08:00
..
detail fix: sync querier schema after column DDL to fix empty query fields (#429) 2026-05-29 17:36:30 +08:00
test_collection.py feat: migrate multi-vector query and reranker logic to C++ (#405) 2026-05-29 10:10:41 +08:00
test_collection_fts.py feat: add fts support (#408) 2026-06-01 15:02:54 +08:00
test_collection_hnsw_rabitq.py deprecate python VectorQuery (#267) 2026-05-12 14:55:49 +08:00
test_convert.py Initial commit 2025-12-30 11:02:17 +08:00
test_doc.py Initial commit 2025-12-30 11:02:17 +08:00
test_embedding.py feat: enlarge topK limit (#348) 2026-04-17 17:51:07 +08:00
test_fts_query.py feat: add fts support (#408) 2026-06-01 15:02:54 +08:00
test_gil_release.py Refactor CPU feature detection to use an explicit x86 whitelist (#258) 2026-06-02 11:51:25 +08:00
test_hnsw_contiguous_memory.py ut: fix some uts (#394) 2026-05-12 19:04:33 +08:00
test_jieba_default_dict.py feat: add fts support (#408) 2026-06-01 15:02:54 +08:00
test_params.py deprecate python VectorQuery (#267) 2026-05-12 14:55:49 +08:00
test_query_executor.py feat: add fts support (#408) 2026-06-01 15:02:54 +08:00
test_reranker.py feat: migrate multi-vector query and reranker logic to C++ (#405) 2026-05-29 10:10:41 +08:00
test_schema.py fix: fix default m (#20) 2026-01-12 10:22:58 +08:00
test_typing.py Initial commit 2025-12-30 11:02:17 +08:00
test_util.py feat: support ai extension (#88) 2026-02-12 18:33:41 +08:00
test_vamana.py ut: fix some uts (#394) 2026-05-12 19:04:33 +08:00