df447a54e2
* fix(cpu_features): refactor architecture detection to explicit x86 whitelist Currently, `cpu_features.cc` assumes any non-ARM architecture is x86/x64, which leads to a fatal missing `<cpuid.h>` error on architectures like RISC-V. This commit refactors the preprocessor macros to explicitly whitelist x86 architectures (`__x86_64__`, `__i386__`, `_M_X64`, `_M_IX86`). All other architectures (RISC-V, ARM, etc.) will now safely fall back to the default zero-initialization, allowing cross-compilation to succeed. Signed-off-by: ihb2032 <hebome@foxmail.com> * ci: Add RISE RISC-V runner Introduce the RISC-V CI runner provided by the RISE project. This enables automated testing and building for the RISC-V architecture. Signed-off-by: ihb2032 <hebome@foxmail.com> * ci: use python 3.12 for RISC-V64 Signed-off-by: ihb2032 <hebome@foxmail.com> * ci: add RISC-V numpy dependencies Signed-off-by: ihb2032 <hebome@foxmail.com> * ci: add RISC-V wheel cache Signed-off-by: ihb2032 <hebome@foxmail.com> * ci: use pre-built RISE numpy wheel to speed up riscv builds Signed-off-by: ihb2032 <hebome@foxmail.com> * ci: use pre-built RISE cmake wheel to speed up riscv builds Signed-off-by: ihb2032 <hebome@foxmail.com> * ci: split RISC-V build and test into separate jobs Signed-off-by: ihb2032 <hebome@foxmail.com> * ci: fix Signed-off-by: ihb2032 <hebome@foxmail.com> * ci: fix Signed-off-by: ihb2032 <hebome@foxmail.com> * Update hnsw_streamer_test.cc * ci: add cache Signed-off-by: ihb2032 <hebome@foxmail.com> * Update hnsw_streamer_test.cc * Update test_gil_release.py * ci: schedule workflow to run overnight --------- Signed-off-by: ihb2032 <hebome@foxmail.com> Co-authored-by: ZeFeng Yin <yinzefeng.yzf@alibaba-inc.com> |
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